The JTAG programmer is a device allowing you to program and debug JTAG enabled devices by the use of a PC.
There are two common JTAG programming approaches, the first one is over parallel port and the second one is over USB. Before we have a brief look at the JTAG programmer let’s introduce some JTAG definitions.
What is JTAG?
The JTAG technology is defined by IEEE Std.-1149.1 standard and it exists for over a decade. The two common fields of use are Connection testing and In System Programming (ISP), below is a simple JTAG device.
The JTAG interface is 4/5-pin interface added to a chip, the interface is so designed that multiple chips having a JTAG interface have their JTAG lines daisy-chained together, and a test probe need only connect to a single “JTAG port” to have access to all chips on a circuit board. The connector pins are
1. TDI (Test Data In)
2. TDO (Test Data Out)
3. TCK (Test Clock)
4. TMS (Test Mode Select)
5. TRST (Test Reset) optional.
Test reset signal is not shown in the image.
Since only one data line is available, the protocol is serial. The clock input is at the TCK pin. Clocking changes on TMS steps through a standardized JTAG state machine. The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register.
This is another “daisy-chained“ JTAG illustration.
- Chain integrity testing
- Interconnection testing between devices
- Core logic testing (BIST)
- In-system programming
- In-Circuit Emulation
- Functional testing
Chain Integrity Testing
The chain integrity testing is based on the fact that each JTAG compliant device contains an ID code, by simply issuing the correct sequence of JTAG commands we can read out all ID codes, simply comparing the actual IDs of the devices the IDs returned from the JTAG chain provides a simple test that the devices are in place and that the JTAG chain is correctly connected.
The connection or interconnect test checks the interconnections between components in a circuit, there are three fault categories; short circuit, open circuit and stuck-at faults.
Connection Test Example
A standard JTAG connection test can only check for faults on nets between JTAG devices, as these are the devices whose pin value can be set and read using JTAG, knowledge of the other, non-JTAG, devices in the circuit can allow for wider test coverage to areas of the circuit away from the JTAG chain.
Many modern programmable devices, such as FPGAs and CPLDs, are designed not only to be JTAG compliant, but also with additional JTAG functionality to allow them to be programmed after they have been attached to the circuit.
Other devices, such as some flash memories, can be programmed indirectly through their connection to devices in the JTAG chain.
The ability to use JTAG to program devices ‘in system’ avoids the need to buy expensive programmers and socketed devices. There is also the advantage of being able to easily update the image held on the device.
Once the physical integrity of the circuit has been verified and devices appropriately programmed, functionality can also be tested.
Some JTAG-compliant devices are designed to incorporate a Built In Self Test (BIST) to test their internal logic. Applying the correct set of signals to the JTAG controller will cause these tests to be executed.